This commit is contained in:
mjallen18
2026-03-13 13:38:53 -05:00
parent 3862a6b651
commit 9737b3af9f
8 changed files with 17 additions and 215 deletions

View File

@@ -50,8 +50,6 @@ in
linuxPackages_cachyos-lts = cachyosPackages.cachyos-lts;
# Steamdeck
linuxPackages_cachyos-deckify = cachyosPackages.cachyos-deckify;
# Asahi (Apple Silicon)
linuxPackages_cachyos-asahi = cachyosPackages.cachyos-asahi;
# Clang Kernels
# Latest
@@ -75,7 +73,5 @@ in
linuxPackages_cachyos-rc-lto-znver4 = cachyosPackages.cachyos-rc-lto-znver4;
# Steamdeck
linuxPackages_cachyos-deckify-lto = cachyosPackages.cachyos-deckify-lto;
# Asahi (Apple Silicon)
linuxPackages_cachyos-asahi-lto = cachyosPackages.cachyos-asahi-lto;
};
}

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@@ -55,7 +55,6 @@ let
ltsVersions = mkVersions (selectVariant versionSpec "lts" null);
rcVersions = mkVersions (selectVariant versionSpec "rc" null);
hardenedVersions = mkVersions (selectVariant versionSpec "hardened" null);
asahiVersions = mkVersions (selectVariant versionSpec "asahi" null);
# ######################################################
# Base LTO Config #
@@ -221,34 +220,6 @@ let
withNTSync = false;
withHDR = false;
};
# ######################################################
# Base Asahi Config #
# ######################################################
asahiAttrs = {
versions = asahiVersions;
# Asahi tracks the 6.18 series; use the LTS config base
taste = "linux-cachyos-asahi";
# Apple Silicon is aarch64-only; no x86 march tuning
mArch = null;
# NTSync and HDR are x86/display-stack features, not applicable here
withNTSync = false;
withHDR = false;
# Enable Rust — required for DRM_ASAHI (AGX GPU) and APPLE_SEP
withRust = true;
# Disable module building extras that don't apply to aarch64 targets
packagesExtend =
_kernel: _final: prev:
prev // { recurseForDerivations = false; };
description = "Linux EEVDF-BORE scheduler Kernel by CachyOS with Asahi Linux patches for Apple Silicon";
};
in
{
inherit
@@ -309,16 +280,6 @@ in
}
);
# Asahi GCC
cachyos-asahi = mkCachyKernel (
gccKernelAttrs
// asahiAttrs
// {
pname = "cachyos-asahi";
configPath = ./config-nix/${arch}-linux/cachyos-lts.${arch}-linux.nix;
}
);
# Deckify GCC
cachyos-deckify = mkCachyKernel (
gccKernelAttrs
@@ -388,16 +349,6 @@ in
}
);
# Asahi LTO
cachyos-asahi-lto = mkCachyKernel (
ltoKernelAttrs
// asahiAttrs
// {
pname = "cachyos-asahi-lto";
configPath = ./config-nix/${arch}-linux/cachyos-lts-lto.${arch}-linux.nix;
}
);
# RC LTO
cachyos-rc-lto = mkCachyKernel (
ltoKernelAttrs

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@@ -19,9 +19,7 @@
}:
let
version =
if cachyConfig.taste == "linux-cachyos-asahi" then
cachyConfig.versions.linux.version
else if stdenv.isAarch64 then
if stdenv.isAarch64 then
"6.12.47"
else
cachyConfig.versions.linux.version;

View File

@@ -1,32 +0,0 @@
From: CachyOS/NixOS-CachyOS
Subject: [PATCH] net/tcp: add TCP_CONG_WANTS_CE_EVENTS for Asahi tree compat
The CachyOS 6.18 base patch adds TCP_CONG_WANTS_CE_EVENTS at BIT(2) and
a tcp_ca_wants_ce_events() helper in include/net/tcp.h, and updates
tcp_bbr.c and tcp_input.c to use them.
The Asahi linux tree already occupies BIT(2)BIT(4) with AccECN flags
(TCP_CONG_NEEDS_ACCECN, TCP_CONG_ECT_1_NEGOTIATION,
TCP_CONG_NO_FALLBACK_RFC3168), so the CachyOS hunk that defines
TCP_CONG_WANTS_CE_EVENTS fails to apply, while the later hunks that
*use* it (tcp_ca_wants_ce_events(), tcp_bbr.c .flags) succeed, leaving
a dangling undefined-identifier compile error.
Fix: define TCP_CONG_WANTS_CE_EVENTS at BIT(5) (the next free bit after
the AccECN flags) and add it to TCP_CONG_MASK. The tcp_ca_wants_ce_events()
helper and tcp_bbr.c / tcp_input.c callers are already in place from the
CachyOS patch, so this is sufficient to resolve the build error.
--- a/include/net/tcp.h
+++ b/include/net/tcp.h
@@ -1198,6 +1198,10 @@ enum tcp_ca_ack_event_flags {
/* Cannot fallback to RFC3168 during AccECN negotiation */
#define TCP_CONG_NO_FALLBACK_RFC3168 BIT(4)
+/* Wants notification of CE events (CA_EVENT_ECN_IS_CE, CA_EVENT_ECN_NO_CE).
+ * BIT(2)BIT(4) are taken by AccECN flags in the Asahi tree. */
+#define TCP_CONG_WANTS_CE_EVENTS BIT(5)
#define TCP_CONG_MASK (TCP_CONG_NON_RESTRICTED | TCP_CONG_NEEDS_ECN | \
- TCP_CONG_NEEDS_ACCECN | TCP_CONG_ECT_1_NEGOTIATION | \
- TCP_CONG_NO_FALLBACK_RFC3168)
+ TCP_CONG_NEEDS_ACCECN | TCP_CONG_ECT_1_NEGOTIATION | \
+ TCP_CONG_NO_FALLBACK_RFC3168 | TCP_CONG_WANTS_CE_EVENTS)

View File

@@ -14,9 +14,7 @@
}:
let
version =
if cachyConfig.taste == "linux-cachyos-asahi" then
cachyConfig.versions.linux.version
else if stdenv.isAarch64 then
if stdenv.isAarch64 then
"6.12.47"
else
cachyConfig.versions.linux.version;
@@ -36,14 +34,7 @@ let
};
src =
if cachyConfig.taste == "linux-cachyos-asahi" then
fetchFromGitHub {
owner = cachyConfig.versions.linux.owner;
repo = cachyConfig.versions.linux.repo;
rev = cachyConfig.versions.linux.rev;
inherit (cachyConfig.versions.linux) hash;
}
else if stdenv.isAarch64 then
if stdenv.isAarch64 then
let
tag = "stable_20250916";
hash = "sha256-Rjn+eWl5cLcc9wgjS3HYVaWM5eKMN3pPfPbsu+QGR/M=";
@@ -95,14 +86,7 @@ let
++ schedPatches
++ lib.optional (
cachyConfig.cpuSched == "hardened"
) "${patches-src}/${majorMinor}/misc/0001-hardened.patch"
# The Asahi tree occupies BIT(2)BIT(4) in TCP_CONG_MASK with AccECN flags,
# so the CachyOS hunk defining TCP_CONG_WANTS_CE_EVENTS at BIT(2) fails to
# apply while later hunks that use it succeed — causing a compile error.
# This patch places the symbol at BIT(5) and adds it to TCP_CONG_MASK.
++ lib.optional (
cachyConfig.taste == "linux-cachyos-asahi"
) ./patches/asahi-tcp-cong-wants-ce-events.patch;
) "${patches-src}/${majorMinor}/misc/0001-hardened.patch";
# There are some configurations set by the PKGBUILD
pkgbuildConfig =
@@ -111,10 +95,9 @@ let
++ mArchConfig
++ cpuSchedConfig
++ [
"-m BCACHEFS_FS"
"-m CONFIG_CRYPTO_BLAKE2B"
]
# _nr_cpus — skip for Asahi; asahiPlatformConfig sets the correct value (64)
++ lib.optional (cachyConfig.taste != "linux-cachyos-asahi") "--set-val NR_CPUS 320"
++ [
# _per_gov, defaults to empty [but PERSONAL CHANGE to "y"]
@@ -154,15 +137,12 @@ let
"-e PER_VMA_LOCK"
"-d PER_VMA_LOCK_STATS"
]
# bcachefs is not in the Asahi 6.18 tree
++ lib.optional (cachyConfig.taste != "linux-cachyos-asahi") "-m BCACHEFS_FS"
++ hugePagesConfig
++ damonConfig
++ ntSyncConfig
++ hdrConfig
++ disableDebug
++ pageSizeConfig
++ asahiPlatformConfig;
++ pageSizeConfig;
# _cachy_config, defaults to "y"
basicCachyConfig = lib.optional cachyConfig.basicCachy "-e CACHY";
@@ -421,84 +401,6 @@ let
else
throw "Unsupported cachyos _hugepage";
# Apple Silicon (Asahi) platform drivers
# Mirrors the options set in the asahi-alarm/PKGBUILDs linux-asahi config.
# ARCH_APPLE is the root Kconfig symbol; everything else gates on it.
# olddefconfig will auto-select most sub-options once ARCH_APPLE is on,
# but the hardware-specific drivers are listed explicitly so they aren't
# left as =m when we want them built-in, or omitted entirely.
asahiPlatformConfig = lib.optionals (cachyConfig.taste == "linux-cachyos-asahi") [
# Rust support — must come before any symbol that depends on it
"-e RUST"
# SoC platform — root symbol; must come first
"-e ARCH_APPLE"
# Interrupt controller
"-e APPLE_AIC"
# IOMMU (required for PCIe, GPU, and NVMe)
"-e APPLE_DART"
# RTKit coprocessor framework (required by GPU, audio, SEP)
"-e APPLE_RTKIT"
"-e APPLE_RTKIT_HELPER"
"-e APPLE_MAILBOX"
# Rust-based mailbox/rtkit (present in 6.18 Asahi tree)
"-e RUST_APPLE_MAILBOX"
"-e RUST_APPLE_RTKIT"
# Power management
"-e APPLE_PMGR_PWRSTATE"
"-e APPLE_PMGR_MISC"
# DMA controller (required by audio)
"-e APPLE_ADMAC"
# Security / SART (required by NVMe)
"-e APPLE_SART"
"-e APPLE_SEP"
# Storage
"-e NVME_APPLE"
# PCIe
"-e PCIE_APPLE"
# CPU frequency / idle
"-e ARM_APPLE_SOC_CPUFREQ"
"-e ARM_APPLE_CPUIDLE"
# Pin control
"-e PINCTRL_APPLE_GPIO"
# Display (DCP)
"-m DRM_APPLE"
"-e DRM_APPLE_AUDIO"
# GPU (Asahi AGX Rust driver)
"-e DRM_ASAHI"
# Audio
"-m SND_SOC_APPLE_MCA"
"-m SND_SOC_APPLE_MACAUDIO"
"-m SND_SOC_APPLE_AOP_AUDIO"
# Misc Apple SoC peripherals
"-e APPLE_DOCKCHANNEL"
"-e APPLE_WATCHDOG"
"-m APPLE_SIO"
"-m APPLE_AOP"
"-e APPLE_M1_CPU_PMU"
# 16K pages — Apple Silicon runs with 16K page granule
"-d ARM64_4K_PAGES"
"-e ARM64_16K_PAGES"
# NR_CPUS: Apple Silicon has at most ~16 cores; 64 is the Asahi default
"--set-val NR_CPUS 64"
];
# _damon, defaults to empty
damonConfig = lib.optionals cachyConfig.withDAMON [
"-e DAMON"
@@ -538,9 +440,8 @@ let
"-d LATENCYTOP"
"-d DEBUG_PREEMPT"
];
# Asahi uses the LTS config base since it tracks the same 6.18 kernel series
configTaste =
if cachyConfig.taste == "linux-cachyos-asahi" then "linux-cachyos-lts" else cachyConfig.taste;
configTaste = cachyConfig.taste;
# Rust toolchain — needed so `make olddefconfig` can probe rustc and set
# RUSTC_VERSION correctly, which gates CONFIG_RUST and all rust-dependent

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@@ -6,15 +6,15 @@
"sources": {
"linux": {
"fetcher": "none",
"version": "6.19.7",
"hash": "sha256-AsGHi4P1+esPCNw4UpM+1tsv8xpfPpCGdOF5XN9glS4="
"version": "6.19.8",
"hash": "sha256-qtpHItuLz6C5cyhRhW1AUIK2pPouOrBnvo2xfN0RWzg="
},
"config": {
"fetcher": "github",
"owner": "CachyOS",
"repo": "linux-cachyos",
"rev": "261b59ccef1a9ca6a3a6344f585ee1ff593e4306",
"hash": "sha256-Z+r3HFziyn0ExgJj8qkwoqPZwP8sQMESX6QBWa/8uwM="
"rev": "3b9ae1ae5d4ee95e1509d350b65c0777dde97628",
"hash": "sha256-O5Fr6f+iS+IVKdB59yqkCaWfkr1SSHD5BLDDlZO7RwU="
},
"patches": {
"fetcher": "github",
@@ -46,8 +46,8 @@
"lts": {
"sources": {
"linux": {
"version": "6.18.17",
"hash": "sha256-K/+XqwWQvFzN1bgihtXvMkgoZyEm693IjQYuOsZa+A0="
"version": "6.18.18",
"hash": "sha256-1iESL16K7Y/Ljljwsy4nkP2Trd6qmFN6HJD/oxjLVXM="
}
}
},
@@ -63,8 +63,8 @@
"hardened": {
"sources": {
"linux": {
"version": "6.18.17",
"hash": "sha256-K/+XqwWQvFzN1bgihtXvMkgoZyEm693IjQYuOsZa+A0="
"version": "6.18.18",
"hash": "sha256-1iESL16K7Y/Ljljwsy4nkP2Trd6qmFN6HJD/oxjLVXM="
}
}
}

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@@ -53,16 +53,4 @@ in
];
};
};
specialisation =
let
kernel = pkgs.${namespace}.linuxPackages_cachyos-asahi-lto;
in
{
"cachyos-asahi".configuration = {
boot = {
kernelPackages = lib.mkOverride 90 kernel;
};
};
};
}

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@@ -4,7 +4,7 @@
...
}:
let
kernel = pkgs.${namespace}.linuxPackages_cachyos-server-lto-znver4;
kernel = pkgs.${namespace}.linuxPackages_cachyos-lto-znver4;
in
{
# Configure bootloader with lanzaboot and secureboot