From 8d8d28f2e5f2c2d0ceb8ac6695575608d6d3eda5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Mario=20B=C4=83l=C4=83nic=C4=83?= Date: Fri, 5 Jan 2024 19:17:57 +0200 Subject: [PATCH 12/16] Platform/RPi5: Enable RNG MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Mario Bălănică --- Platform/RaspberryPi/RPi4/RPi4.dsc | 5 +++++ Platform/RaspberryPi/RPi5/RPi5.dsc | 7 +++++- Platform/RaspberryPi/RPi5/RPi5.fdf | 2 +- Silicon/Broadcom/Bcm283x/Bcm283x.dec | 1 + .../Drivers/Bcm2838RngDxe/Bcm2838RngDxe.c | 14 +++++++----- .../Drivers/Bcm2838RngDxe/Bcm2838RngDxe.inf | 2 +- .../Include/IndustryStandard/Bcm2838Rng.h | 22 ++++++++----------- 7 files changed, 32 insertions(+), 21 deletions(-) diff --git a/Platform/RaspberryPi/RPi4/RPi4.dsc b/Platform/RaspberryPi/RPi4/RPi4.dsc index a48092c1..02aae204 100644 --- a/Platform/RaspberryPi/RPi4/RPi4.dsc +++ b/Platform/RaspberryPi/RPi4/RPi4.dsc @@ -461,6 +461,11 @@ # gRaspberryPiTokenSpaceGuid.PcdFwMailboxBaseAddress|0xfe00b880 + # + # RNG + # + gBcm283xTokenSpaceGuid.PcdBcm2838RngBaseAddress|0x7e104000 + # # Fixed CPU settings. # diff --git a/Platform/RaspberryPi/RPi5/RPi5.dsc b/Platform/RaspberryPi/RPi5/RPi5.dsc index 15f6e1a3..4f128fe0 100644 --- a/Platform/RaspberryPi/RPi5/RPi5.dsc +++ b/Platform/RaspberryPi/RPi5/RPi5.dsc @@ -438,6 +438,11 @@ # gRaspberryPiTokenSpaceGuid.PcdFwMailboxBaseAddress|0x107c013880 + # + # RNG + # + gBcm283xTokenSpaceGuid.PcdBcm2838RngBaseAddress|0x107d208000 + # # RP1 BAR1 preconfigured by the VPU # @@ -643,7 +648,7 @@ # # RNG # - # Silicon/Broadcom/Bcm283x/Drivers/Bcm2838RngDxe/Bcm2838RngDxe.inf + Silicon/Broadcom/Bcm283x/Drivers/Bcm2838RngDxe/Bcm2838RngDxe.inf # # PCI Support diff --git a/Platform/RaspberryPi/RPi5/RPi5.fdf b/Platform/RaspberryPi/RPi5/RPi5.fdf index 1507e39d..4a5a05f6 100644 --- a/Platform/RaspberryPi/RPi5/RPi5.fdf +++ b/Platform/RaspberryPi/RPi5/RPi5.fdf @@ -278,7 +278,7 @@ READ_LOCK_STATUS = TRUE # # RNG # - # INF Silicon/Broadcom/Bcm283x/Drivers/Bcm2838RngDxe/Bcm2838RngDxe.inf + INF Silicon/Broadcom/Bcm283x/Drivers/Bcm2838RngDxe/Bcm2838RngDxe.inf # # PCI Support diff --git a/Silicon/Broadcom/Bcm283x/Bcm283x.dec b/Silicon/Broadcom/Bcm283x/Bcm283x.dec index 5b839b00..c4f40216 100644 --- a/Silicon/Broadcom/Bcm283x/Bcm283x.dec +++ b/Silicon/Broadcom/Bcm283x/Bcm283x.dec @@ -21,3 +21,4 @@ [PcdsFixedAtBuild.common] gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress|0x0|UINT32|0x00000001 + gBcm283xTokenSpaceGuid.PcdBcm2838RngBaseAddress|0x0|UINT64|0x00000002 diff --git a/Silicon/Broadcom/Bcm283x/Drivers/Bcm2838RngDxe/Bcm2838RngDxe.c b/Silicon/Broadcom/Bcm283x/Drivers/Bcm2838RngDxe/Bcm2838RngDxe.c index 5737876e..ec4ecc0a 100644 --- a/Silicon/Broadcom/Bcm283x/Drivers/Bcm2838RngDxe/Bcm2838RngDxe.c +++ b/Silicon/Broadcom/Bcm283x/Drivers/Bcm2838RngDxe/Bcm2838RngDxe.c @@ -24,6 +24,8 @@ #define RNG_WARMUP_COUNT 0x40000 #define RNG_MAX_RETRIES 0x100 // arbitrary upper bound +STATIC EFI_PHYSICAL_ADDRESS mRngBase; + /** Returns information about the random number generation implementation. @@ -110,7 +112,7 @@ Bcm2838RngReadValue ( ASSERT (Val != NULL); - Avail = MmioRead32 (RNG_FIFO_COUNT) & RNG_FIFO_DATA_AVAIL_MASK; + Avail = MmioRead32 (mRngBase + RNG_FIFO_COUNT) & RNG_FIFO_DATA_AVAIL_MASK; // // If we don't have a value ready, wait 1 us and retry. @@ -131,13 +133,13 @@ Bcm2838RngReadValue ( // for (i = 0; Avail < 1 && i < RNG_MAX_RETRIES; i++) { MicroSecondDelay (1); - Avail = MmioRead32 (RNG_FIFO_COUNT) & RNG_FIFO_DATA_AVAIL_MASK; + Avail = MmioRead32 (mRngBase + RNG_FIFO_COUNT) & RNG_FIFO_DATA_AVAIL_MASK; } if (Avail < 1) { return EFI_NOT_READY; } - *Val = MmioRead32 (RNG_FIFO_DATA); + *Val = MmioRead32 (mRngBase + RNG_FIFO_DATA); return EFI_SUCCESS; } @@ -246,6 +248,8 @@ Bcm2838RngEntryPoint ( { EFI_STATUS Status; + mRngBase = PcdGet64 (PcdBcm2838RngBaseAddress); + Status = gBS->InstallMultipleProtocolInterfaces (&ImageHandle, &gEfiRngProtocolGuid, &mBcm2838RngProtocol, NULL); @@ -257,7 +261,7 @@ Bcm2838RngEntryPoint ( // This results in the RNG holding off from populating any value into the // FIFO until the value below has been reached in RNG_BIT_COUNT. // - MmioWrite32 (RNG_BIT_COUNT_THRESHOLD, RNG_WARMUP_COUNT); + MmioWrite32 (mRngBase + RNG_BIT_COUNT_THRESHOLD, RNG_WARMUP_COUNT); // // We would disable RNG interrupts here... if we had access to the datasheet. @@ -278,7 +282,7 @@ Bcm2838RngEntryPoint ( // instead of single bits, which may be unintended. But since we don't have // any public documentation on what each of these bits do, we follow suit. // - MmioWrite32 (RNG_CTRL, + MmioWrite32 (mRngBase + RNG_CTRL, RNG_CTRL_ENABLE_MASK | (3 << RNG_CTRL_SAMPLE_RATE_DIVISOR_SHIFT)); return EFI_SUCCESS; diff --git a/Silicon/Broadcom/Bcm283x/Drivers/Bcm2838RngDxe/Bcm2838RngDxe.inf b/Silicon/Broadcom/Bcm283x/Drivers/Bcm2838RngDxe/Bcm2838RngDxe.inf index fdc1b257..dadd5765 100644 --- a/Silicon/Broadcom/Bcm283x/Drivers/Bcm2838RngDxe/Bcm2838RngDxe.inf +++ b/Silicon/Broadcom/Bcm283x/Drivers/Bcm2838RngDxe/Bcm2838RngDxe.inf @@ -40,7 +40,7 @@ gEfiRngAlgorithmRaw [FixedPcd] - gBcm283xTokenSpaceGuid.PcdBcm283xRegistersAddress + gBcm283xTokenSpaceGuid.PcdBcm2838RngBaseAddress [Depex] TRUE diff --git a/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2838Rng.h b/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2838Rng.h index 003866fa..8b321151 100644 --- a/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2838Rng.h +++ b/Silicon/Broadcom/Bcm283x/Include/IndustryStandard/Bcm2838Rng.h @@ -9,19 +9,15 @@ #ifndef BCM2838_RNG_H__ #define BCM2838_RNG_H__ -#define BCM2838_RNG_OFFSET 0x00104000 -#define RNG_BASE_ADDRESS ((FixedPcdGet64 (PcdBcm283xRegistersAddress)) \ - + BCM2838_RNG_OFFSET) - -#define RNG_CTRL (RNG_BASE_ADDRESS + 0x0) -#define RNG_STATUS (RNG_BASE_ADDRESS + 0x4) -#define RNG_DATA (RNG_BASE_ADDRESS + 0x8) -#define RNG_BIT_COUNT (RNG_BASE_ADDRESS + 0xc) -#define RNG_BIT_COUNT_THRESHOLD (RNG_BASE_ADDRESS + 0x10) -#define RNG_INT_STATUS (RNG_BASE_ADDRESS + 0x18) -#define RNG_INT_ENABLE (RNG_BASE_ADDRESS + 0x1c) -#define RNG_FIFO_DATA (RNG_BASE_ADDRESS + 0x20) -#define RNG_FIFO_COUNT (RNG_BASE_ADDRESS + 0x24) +#define RNG_CTRL 0x0 +#define RNG_STATUS 0x4 +#define RNG_DATA 0x8 +#define RNG_BIT_COUNT 0xc +#define RNG_BIT_COUNT_THRESHOLD 0x10 +#define RNG_INT_STATUS 0x18 +#define RNG_INT_ENABLE 0x1c +#define RNG_FIFO_DATA 0x20 +#define RNG_FIFO_COUNT 0x24 #define RNG_CTRL_ENABLE_MASK 0x1fff #define RNG_CTRL_SAMPLE_RATE_DIVISOR_SHIFT 13 // Unmasked bits from above -- 2.51.2