From 297f8d44c47ba57b6a7f205a502cc34210050a7a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Mario=20B=C4=83l=C4=83nic=C4=83?= Date: Fri, 29 Dec 2023 04:17:13 +0200 Subject: [PATCH 06/16] Silicon/Bcm2712: Add GPIO support library MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Mario Bălănică --- .../Include/IndustryStandard/Bcm2712.h | 22 + .../Include/IndustryStandard/Bcm2712Pinctrl.h | 764 ++++++++++++++++++ .../Bcm27xx/Include/Library/Bcm2712GpioLib.h | 103 +++ .../Library/Bcm2712GpioLib/Bcm2712GpioLib.c | 375 +++++++++ .../Library/Bcm2712GpioLib/Bcm2712GpioLib.inf | 26 + 5 files changed, 1290 insertions(+) create mode 100644 Silicon/Broadcom/Bcm27xx/Include/IndustryStandard/Bcm2712.h create mode 100644 Silicon/Broadcom/Bcm27xx/Include/IndustryStandard/Bcm2712Pinctrl.h create mode 100644 Silicon/Broadcom/Bcm27xx/Include/Library/Bcm2712GpioLib.h create mode 100644 Silicon/Broadcom/Bcm27xx/Library/Bcm2712GpioLib/Bcm2712GpioLib.c create mode 100644 Silicon/Broadcom/Bcm27xx/Library/Bcm2712GpioLib/Bcm2712GpioLib.inf diff --git a/Silicon/Broadcom/Bcm27xx/Include/IndustryStandard/Bcm2712.h b/Silicon/Broadcom/Bcm27xx/Include/IndustryStandard/Bcm2712.h new file mode 100644 index 00000000..a0d3e850 --- /dev/null +++ b/Silicon/Broadcom/Bcm27xx/Include/IndustryStandard/Bcm2712.h @@ -0,0 +1,22 @@ +/** @file + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef __BCM2712_H__ +#define __BCM2712_H__ + +#define BCM2712_BRCMSTB_GIO_BASE 0x107d508500 +#define BCM2712_BRCMSTB_GIO_LENGTH 0x40 +#define BCM2712_BRCMSTB_GIO_AON_BASE 0x107d517c00 +#define BCM2712_BRCMSTB_GIO_AON_LENGTH 0x40 + +#define BCM2712_PINCTRL_BASE 0x107d504100 +#define BCM2712_PINCTRL_LENGTH 0x30 +#define BCM2712_PINCTRL_AON_BASE 0x107d510700 +#define BCM2712_PINCTRL_AON_LENGTH 0x20 + +#endif // __BCM2712_H__ diff --git a/Silicon/Broadcom/Bcm27xx/Include/IndustryStandard/Bcm2712Pinctrl.h b/Silicon/Broadcom/Bcm27xx/Include/IndustryStandard/Bcm2712Pinctrl.h new file mode 100644 index 00000000..12c47999 --- /dev/null +++ b/Silicon/Broadcom/Bcm27xx/Include/IndustryStandard/Bcm2712Pinctrl.h @@ -0,0 +1,764 @@ +/** @file + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#ifndef __BCM2712_PINCTRL_H__ +#define __BCM2712_PINCTRL_H__ + +// +// Supported Alternate Pin Functions +// + +// +// General Input/Output (GIO) +// +typedef enum { + GIO_PIN0_ALT_BSC_M3 = 1, + GIO_PIN0_ALT_VC_I2C0, + GIO_PIN0_ALT_GPCLK0, + GIO_PIN0_ALT_ENET0, + GIO_PIN0_ALT_VC_PWM1, + GIO_PIN0_ALT_VC_SPI0, + GIO_PIN0_ALT_IR_IN, +} GIO_PIN0_ALT; + +typedef enum { + GIO_PIN1_ALT_BSC_M3 = 1, + GIO_PIN1_ALT_VC_I2C0, + GIO_PIN1_ALT_GPCLK1, + GIO_PIN1_ALT_ENET0, + GIO_PIN1_ALT_VC_PWM1, + GIO_PIN1_ALT_SR_EDM_SENSE, + GIO_PIN1_ALT_VC_SPI0, + GIO_PIN1_ALT_VC_UART3, +} GIO_PIN1_ALT; + +typedef enum { + GIO_PIN2_ALT_PDM = 1, + GIO_PIN2_ALT_I2S_IN, + GIO_PIN2_ALT_GPCLK2, + GIO_PIN2_ALT_VC_SPI4, + GIO_PIN2_ALT_PKT, + GIO_PIN2_ALT_VC_SPI0, + GIO_PIN2_ALT_VC_UART3, +} GIO_PIN2_ALT; + +typedef enum { + GIO_PIN3_ALT_PDM = 1, + GIO_PIN3_ALT_I2S_IN, + GIO_PIN3_ALT_VC_SPI4, + GIO_PIN3_ALT_PKT, + GIO_PIN3_ALT_VC_SPI0, + GIO_PIN3_ALT_VC_UART3, +} GIO_PIN3_ALT; + +typedef enum { + GIO_PIN4_ALT_PDM = 1, + GIO_PIN4_ALT_I2S_IN, + GIO_PIN4_ALT_ARM_JTAG, + GIO_PIN4_ALT_VC_SPI4, + GIO_PIN4_ALT_PKT, + GIO_PIN4_ALT_VC_SPI0, + GIO_PIN4_ALT_VC_UART3, +} GIO_PIN4_ALT; + +typedef enum { + GIO_PIN5_ALT_PDM = 1, + GIO_PIN5_ALT_VC_I2C3, + GIO_PIN5_ALT_ARM_JTAG, + GIO_PIN5_ALT_SD_CARD_E, + GIO_PIN5_ALT_VC_SPI4, + GIO_PIN5_ALT_PKT, + GIO_PIN5_ALT_VC_PCM, + GIO_PIN5_ALT_VC_I2C5, +} GIO_PIN5_ALT; + +typedef enum { + GIO_PIN6_ALT_PDM = 1, + GIO_PIN6_ALT_VC_I2C3, + GIO_PIN6_ALT_ARM_JTAG, + GIO_PIN6_ALT_SD_CARD_E, + GIO_PIN6_ALT_VC_SPI4, + GIO_PIN6_ALT_PKT, + GIO_PIN6_ALT_VC_PCM, + GIO_PIN6_ALT_VC_I2C5, +} GIO_PIN6_ALT; + +typedef enum { + GIO_PIN7_ALT_I2S_OUT = 1, + GIO_PIN7_ALT_SPDIF_OUT, + GIO_PIN7_ALT_ARM_JTAG, + GIO_PIN7_ALT_SD_CARD_E, + GIO_PIN7_ALT_VC_I2C3, + GIO_PIN7_ALT_ENET0_RGMII, + GIO_PIN7_ALT_VC_PCM, + GIO_PIN7_ALT_VC_SPI4, +} GIO_PIN7_ALT; + +typedef enum { + GIO_PIN8_ALT_I2S_OUT = 1, + GIO_PIN8_ALT_AUD_FS_CLK0, + GIO_PIN8_ALT_ARM_JTAG, + GIO_PIN8_ALT_SD_CARD_E, + GIO_PIN8_ALT_VC_I2C3, + GIO_PIN8_ALT_ENET0_MII, + GIO_PIN8_ALT_VC_PCM, + GIO_PIN8_ALT_VC_SPI4, +} GIO_PIN8_ALT; + +typedef enum { + GIO_PIN9_ALT_I2S_OUT = 1, + GIO_PIN9_ALT_AUD_FS_CLK0, + GIO_PIN9_ALT_ARM_JTAG, + GIO_PIN9_ALT_SD_CARD_E, + GIO_PIN9_ALT_ENET0_MII, + GIO_PIN9_ALT_SD_CARD_C, + GIO_PIN9_ALT_VC_SPI4, +} GIO_PIN9_ALT; + +typedef enum { + GIO_PIN10_ALT_BSC_M3 = 1, + GIO_PIN10_ALT_MTSIF_ALT1, + GIO_PIN10_ALT_I2S_IN, + GIO_PIN10_ALT_I2S_OUT, + GIO_PIN10_ALT_VC_SPI5, + GIO_PIN10_ALT_ENET0_MII, + GIO_PIN10_ALT_SD_CARD_C, + GIO_PIN10_ALT_VC_SPI4, +} GIO_PIN10_ALT; + +typedef enum { + GIO_PIN11_ALT_BSC_M3 = 1, + GIO_PIN11_ALT_MTSIF_ALT1, + GIO_PIN11_ALT_I2S_IN, + GIO_PIN11_ALT_I2S_OUT, + GIO_PIN11_ALT_VC_SPI5, + GIO_PIN11_ALT_ENET0_MII, + GIO_PIN11_ALT_SD_CARD_C, + GIO_PIN11_ALT_VC_SPI4, +} GIO_PIN11_ALT; + +typedef enum { + GIO_PIN12_ALT_SPI_S = 1, + GIO_PIN12_ALT_MTSIF_ALT1, + GIO_PIN12_ALT_I2S_IN, + GIO_PIN12_ALT_I2S_OUT, + GIO_PIN12_ALT_VC_SPI5, + GIO_PIN12_ALT_VC_I2CSL, + GIO_PIN12_ALT_SD0, + GIO_PIN12_ALT_SD_CARD_D, +} GIO_PIN12_ALT; + +typedef enum { + GIO_PIN13_ALT_SPI_S = 1, + GIO_PIN13_ALT_MTSIF_ALT1, + GIO_PIN13_ALT_I2S_OUT, + GIO_PIN13_ALT_USB_VBUS, + GIO_PIN13_ALT_VC_SPI5, + GIO_PIN13_ALT_VC_I2CSL, + GIO_PIN13_ALT_SD0, + GIO_PIN13_ALT_SD_CARD_D, +} GIO_PIN13_ALT; + +typedef enum { + GIO_PIN14_ALT_SPI_S = 1, + GIO_PIN14_ALT_VC_I2CSL, + GIO_PIN14_ALT_ENET0_RGMII, + GIO_PIN14_ALT_ARM_JTAG, + GIO_PIN14_ALT_VC_SPI5, + GIO_PIN14_ALT_VC_PWM0, + GIO_PIN14_ALT_VC_I2C4, + GIO_PIN14_ALT_SD_CARD_D, +} GIO_PIN14_ALT; + +typedef enum { + GIO_PIN15_ALT_SPI_S = 1, + GIO_PIN15_ALT_VC_I2CSL, + GIO_PIN15_ALT_VC_SPI3, + GIO_PIN15_ALT_ARM_JTAG, + GIO_PIN15_ALT_VC_PWM0, + GIO_PIN15_ALT_VC_I2C4, + GIO_PIN15_ALT_GPCLK0, +} GIO_PIN15_ALT; + +typedef enum { + GIO_PIN16_ALT_SD_CARD_B = 1, + GIO_PIN16_ALT_I2S_OUT, + GIO_PIN16_ALT_VC_SPI3, + GIO_PIN16_ALT_I2S_IN, + GIO_PIN16_ALT_SD0, + GIO_PIN16_ALT_ENET0_RGMII, + GIO_PIN16_ALT_GPCLK1, +} GIO_PIN16_ALT; + +typedef enum { + GIO_PIN17_ALT_SD_CARD_B = 1, + GIO_PIN17_ALT_I2S_OUT, + GIO_PIN17_ALT_VC_SPI3, + GIO_PIN17_ALT_I2S_IN, + GIO_PIN17_ALT_EXT_SC_CLK, + GIO_PIN17_ALT_SD0, + GIO_PIN17_ALT_ENET0_RGMII, + GIO_PIN17_ALT_GPCLK2, +} GIO_PIN17_ALT; + +typedef enum { + GIO_PIN18_ALT_SD_CARD_B = 1, + GIO_PIN18_ALT_I2S_OUT, + GIO_PIN18_ALT_VC_SPI3, + GIO_PIN18_ALT_I2S_IN, + GIO_PIN18_ALT_SD0, + GIO_PIN18_ALT_ENET0_RGMII, + GIO_PIN18_ALT_VC_PWM1, +} GIO_PIN18_ALT; + +typedef enum { + GIO_PIN19_ALT_SD_CARD_B = 1, + GIO_PIN19_ALT_USB_PWR, + GIO_PIN19_ALT_VC_SPI3, + GIO_PIN19_ALT_PKT, + GIO_PIN19_ALT_SPDIF_OUT, + GIO_PIN19_ALT_SD0, + GIO_PIN19_ALT_IR_IN, + GIO_PIN19_ALT_VC_PWM1, +} GIO_PIN19_ALT; + +typedef enum { + GIO_PIN20_ALT_SD_CARD_B = 1, + GIO_PIN20_ALT_UUI, + GIO_PIN20_ALT_VC_UART0, + GIO_PIN20_ALT_ARM_JTAG, + GIO_PIN20_ALT_UART2, + GIO_PIN20_ALT_USB_PWR, + GIO_PIN20_ALT_VC_PCM, + GIO_PIN20_ALT_VC_UART4, +} GIO_PIN20_ALT; + +typedef enum { + GIO_PIN21_ALT_USB_PWR = 1, + GIO_PIN21_ALT_UUI, + GIO_PIN21_ALT_VC_UART0, + GIO_PIN21_ALT_ARM_JTAG, + GIO_PIN21_ALT_UART2, + GIO_PIN21_ALT_SD_CARD_B, + GIO_PIN21_ALT_VC_PCM, + GIO_PIN21_ALT_VC_UART4, +} GIO_PIN21_ALT; + +typedef enum { + GIO_PIN22_ALT_USB_PWR = 1, + GIO_PIN22_ALT_ENET0, + GIO_PIN22_ALT_VC_UART0, + GIO_PIN22_ALT_MTSIF, + GIO_PIN22_ALT_UART2, + GIO_PIN22_ALT_USB_VBUS, + GIO_PIN22_ALT_VC_PCM, + GIO_PIN22_ALT_VC_I2C5, +} GIO_PIN22_ALT; + +typedef enum { + GIO_PIN23_ALT_USB_VBUS = 1, + GIO_PIN23_ALT_ENET0, + GIO_PIN23_ALT_VC_UART0, + GIO_PIN23_ALT_MTSIF, + GIO_PIN23_ALT_UART2, + GIO_PIN23_ALT_I2S_OUT, + GIO_PIN23_ALT_VC_PCM, + GIO_PIN23_ALT_VC_I2C5, +} GIO_PIN23_ALT; + +typedef enum { + GIO_PIN24_ALT_MTSIF = 1, + GIO_PIN24_ALT_PKT, + GIO_PIN24_ALT_UART0, + GIO_PIN24_ALT_ENET0_RGMII, + GIO_PIN24_ALT_ENET0_RGMII_2, + GIO_PIN24_ALT_VC_I2C4, + GIO_PIN24_ALT_VC_UART3, +} GIO_PIN24_ALT; + +typedef enum { + GIO_PIN25_ALT_MTSIF = 1, + GIO_PIN25_ALT_PKT, + GIO_PIN25_ALT_SC0, + GIO_PIN25_ALT_UART0, + GIO_PIN25_ALT_ENET0_RGMII, + GIO_PIN25_ALT_ENET0_RGMII_2, + GIO_PIN25_ALT_VC_I2C4, + GIO_PIN25_ALT_VC_UART3, +} GIO_PIN25_ALT; + +typedef enum { + GIO_PIN26_ALT_MTSIF = 1, + GIO_PIN26_ALT_PKT, + GIO_PIN26_ALT_SC0, + GIO_PIN26_ALT_UART0, + GIO_PIN26_ALT_ENET0_RGMII, + GIO_PIN26_ALT_VC_UART4, + GIO_PIN26_ALT_VC_SPI5, +} GIO_PIN26_ALT; + +typedef enum { + GIO_PIN27_ALT_MTSIF = 1, + GIO_PIN27_ALT_PKT, + GIO_PIN27_ALT_SC0, + GIO_PIN27_ALT_UART0, + GIO_PIN27_ALT_ENET0_RGMII, + GIO_PIN27_ALT_VC_UART4, + GIO_PIN27_ALT_VC_SPI5, +} GIO_PIN27_ALT; + +typedef enum { + GIO_PIN28_ALT_MTSIF = 1, + GIO_PIN28_ALT_PKT, + GIO_PIN28_ALT_SC0, + GIO_PIN28_ALT_ENET0_RGMII, + GIO_PIN28_ALT_VC_UART4, + GIO_PIN28_ALT_VC_SPI5, +} GIO_PIN28_ALT; + +typedef enum { + GIO_PIN29_ALT_MTSIF = 1, + GIO_PIN29_ALT_PKT, + GIO_PIN29_ALT_SC0, + GIO_PIN29_ALT_ENET0_RGMII, + GIO_PIN29_ALT_VC_UART4, + GIO_PIN29_ALT_VC_SPI5, +} GIO_PIN29_ALT; + +typedef enum { + GIO_PIN30_ALT_MTSIF = 1, + GIO_PIN30_ALT_PKT, + GIO_PIN30_ALT_SC0, + GIO_PIN30_ALT_SD2, + GIO_PIN30_ALT_ENET0_RGMII, + GIO_PIN30_ALT_GPCLK0, + GIO_PIN30_ALT_VC_PWM0, +} GIO_PIN30_ALT; + +typedef enum { + GIO_PIN31_ALT_MTSIF = 1, + GIO_PIN31_ALT_PKT, + GIO_PIN31_ALT_SC0, + GIO_PIN31_ALT_SD2, + GIO_PIN31_ALT_ENET0_RGMII, + GIO_PIN31_ALT_VC_SPI3, + GIO_PIN31_ALT_VC_PWM0, +} GIO_PIN31_ALT; + +typedef enum { + GIO_PIN32_ALT_MTSIF = 1, + GIO_PIN32_ALT_PKT, + GIO_PIN32_ALT_SC0, + GIO_PIN32_ALT_SD2, + GIO_PIN32_ALT_ENET0_RGMII, + GIO_PIN32_ALT_VC_SPI3, + GIO_PIN32_ALT_VC_UART3, +} GIO_PIN32_ALT; + +typedef enum { + GIO_PIN33_ALT_MTSIF = 1, + GIO_PIN33_ALT_PKT, + GIO_PIN33_ALT_SD2, + GIO_PIN33_ALT_ENET0_RGMII, + GIO_PIN33_ALT_VC_SPI3, + GIO_PIN33_ALT_VC_UART3, +} GIO_PIN33_ALT; + +typedef enum { + GIO_PIN34_ALT_MTSIF = 1, + GIO_PIN34_ALT_PKT, + GIO_PIN34_ALT_EXT_SC_CLK, + GIO_PIN34_ALT_SD2, + GIO_PIN34_ALT_ENET0_RGMII, + GIO_PIN34_ALT_VC_SPI3, + GIO_PIN34_ALT_VC_I2C5, +} GIO_PIN34_ALT; + +typedef enum { + GIO_PIN35_ALT_MTSIF = 1, + GIO_PIN35_ALT_PKT, + GIO_PIN35_ALT_SD2, + GIO_PIN35_ALT_ENET0_RGMII, + GIO_PIN35_ALT_VC_SPI3, + GIO_PIN35_ALT_VC_I2C5, +} GIO_PIN35_ALT; + +typedef enum { + GIO_PIN36_ALT_SD0 = 1, + GIO_PIN36_ALT_MTSIF, + GIO_PIN36_ALT_SC0, + GIO_PIN36_ALT_I2S_IN, + GIO_PIN36_ALT_VC_UART3, + GIO_PIN36_ALT_VC_UART2, +} GIO_PIN36_ALT; + +typedef enum { + GIO_PIN37_ALT_SD0 = 1, + GIO_PIN37_ALT_MTSIF, + GIO_PIN37_ALT_SC0, + GIO_PIN37_ALT_VC_SPI0, + GIO_PIN37_ALT_I2S_IN, + GIO_PIN37_ALT_VC_UART3, + GIO_PIN37_ALT_VC_UART2, +} GIO_PIN37_ALT; + +typedef enum { + GIO_PIN38_ALT_SD0 = 1, + GIO_PIN38_ALT_MTSIF_ALT, + GIO_PIN38_ALT_SC0, + GIO_PIN38_ALT_VC_SPI0, + GIO_PIN38_ALT_I2S_IN, + GIO_PIN38_ALT_VC_UART3, + GIO_PIN38_ALT_VC_UART2, +} GIO_PIN38_ALT; + +typedef enum { + GIO_PIN39_ALT_SD0 = 1, + GIO_PIN39_ALT_MTSIF_ALT, + GIO_PIN39_ALT_SC0, + GIO_PIN39_ALT_VC_SPI0, + GIO_PIN39_ALT_VC_UART3, + GIO_PIN39_ALT_VC_UART2, +} GIO_PIN39_ALT; + +typedef enum { + GIO_PIN40_ALT_SD0 = 1, + GIO_PIN40_ALT_MTSIF_ALT, + GIO_PIN40_ALT_SC0, + GIO_PIN40_ALT_VC_SPI0, + GIO_PIN40_ALT_BSC_M3, +} GIO_PIN40_ALT; + +typedef enum { + GIO_PIN41_ALT_SD0 = 1, + GIO_PIN41_ALT_MTSIF_ALT, + GIO_PIN41_ALT_SC0, + GIO_PIN41_ALT_VC_SPI0, + GIO_PIN41_ALT_BSC_M3, +} GIO_PIN41_ALT; + +typedef enum { + GIO_PIN42_ALT_VC_SPI0 = 1, + GIO_PIN42_ALT_MTSIF_ALT, + GIO_PIN42_ALT_VC_I2C0, + GIO_PIN42_ALT_SD_CARD_A, + GIO_PIN42_ALT_MTSIF_ALT1, + GIO_PIN42_ALT_ARM_JTAG, + GIO_PIN42_ALT_PDM, + GIO_PIN42_ALT_SPI_M, +} GIO_PIN42_ALT; + +typedef enum { + GIO_PIN43_ALT_VC_SPI0 = 1, + GIO_PIN43_ALT_MTSIF_ALT, + GIO_PIN43_ALT_VC_I2C0, + GIO_PIN43_ALT_SD_CARD_A, + GIO_PIN43_ALT_MTSIF_ALT1, + GIO_PIN43_ALT_ARM_JTAG, + GIO_PIN43_ALT_PDM, + GIO_PIN43_ALT_SPI_M, +} GIO_PIN43_ALT; + +typedef enum { + GIO_PIN44_ALT_VC_SPI0 = 1, + GIO_PIN44_ALT_MTSIF_ALT, + GIO_PIN44_ALT_ENET0, + GIO_PIN44_ALT_SD_CARD_A, + GIO_PIN44_ALT_MTSIF_ALT1, + GIO_PIN44_ALT_ARM_JTAG, + GIO_PIN44_ALT_PDM, + GIO_PIN44_ALT_SPI_M, +} GIO_PIN44_ALT; + +typedef enum { + GIO_PIN45_ALT_VC_SPI0 = 1, + GIO_PIN45_ALT_MTSIF_ALT, + GIO_PIN45_ALT_ENET0, + GIO_PIN45_ALT_SD_CARD_A, + GIO_PIN45_ALT_MTSIF_ALT1, + GIO_PIN45_ALT_ARM_JTAG, + GIO_PIN45_ALT_PDM, + GIO_PIN45_ALT_SPI_M, +} GIO_PIN45_ALT; + +typedef enum { + GIO_PIN46_ALT_VC_SPI0 = 1, + GIO_PIN46_ALT_MTSIF_ALT, + GIO_PIN46_ALT_SD_CARD_A, + GIO_PIN46_ALT_MTSIF_ALT1, + GIO_PIN46_ALT_ARM_JTAG, + GIO_PIN46_ALT_PDM, + GIO_PIN46_ALT_SPI_M, +} GIO_PIN46_ALT; + +typedef enum { + GIO_PIN47_ALT_ENET0 = 1, + GIO_PIN47_ALT_MTSIF_ALT, + GIO_PIN47_ALT_I2S_OUT, + GIO_PIN47_ALT_MTSIF_ALT1, + GIO_PIN47_ALT_ARM_JTAG, +} GIO_PIN47_ALT; + +typedef enum { + GIO_PIN48_ALT_SC0 = 1, + GIO_PIN48_ALT_USB_PWR, + GIO_PIN48_ALT_SPDIF_OUT, + GIO_PIN48_ALT_MTSIF, +} GIO_PIN48_ALT; + +typedef enum { + GIO_PIN49_ALT_SC0 = 1, + GIO_PIN49_ALT_USB_PWR, + GIO_PIN49_ALT_AUD_FS_CLK0, + GIO_PIN49_ALT_MTSIF, +} GIO_PIN49_ALT; + +typedef enum { + GIO_PIN50_ALT_SC0 = 1, + GIO_PIN50_ALT_USB_VBUS, + GIO_PIN50_ALT_SC0_2, +} GIO_PIN50_ALT; + +typedef enum { + GIO_PIN51_ALT_SC0 = 1, + GIO_PIN51_ALT_ENET0, + GIO_PIN51_ALT_SC0_2, + GIO_PIN51_ALT_SR_EDM_SENSE, +} GIO_PIN51_ALT; + +typedef enum { + GIO_PIN52_ALT_SC0 = 1, + GIO_PIN52_ALT_ENET0, + GIO_PIN52_ALT_VC_PWM1, +} GIO_PIN52_ALT; + +typedef enum { + GIO_PIN53_ALT_SC0 = 1, + GIO_PIN53_ALT_ENET0_RGMII, + GIO_PIN53_ALT_EXT_SC_CLK, +} GIO_PIN53_ALT; + +// +// General Input/Output Always ON (GIO AON) +// +typedef enum { + GIO_AON_PIN0_ALT_IR_IN = 1, + GIO_AON_PIN0_ALT_VC_SPI0, + GIO_AON_PIN0_ALT_VC_UART3, + GIO_AON_PIN0_ALT_VC_I2C3, + GIO_AON_PIN0_ALT_TE0, + GIO_AON_PIN0_ALT_VC_I2C0, +} GIO_AON_PIN0_ALT; + +typedef enum { + GIO_AON_PIN1_ALT_VC_PWM0 = 1, + GIO_AON_PIN1_ALT_VC_SPI0, + GIO_AON_PIN1_ALT_VC_UART3, + GIO_AON_PIN1_ALT_VC_I2C3, + GIO_AON_PIN1_ALT_TE1, + GIO_AON_PIN1_ALT_AON_PWM, + GIO_AON_PIN1_ALT_VC_I2C0, + GIO_AON_PIN1_ALT_VC_PWM1, +} GIO_AON_PIN1_ALT; + +typedef enum { + GIO_AON_PIN2_ALT_VC_PWM0 = 1, + GIO_AON_PIN2_ALT_VC_SPI0, + GIO_AON_PIN2_ALT_VC_UART3, + GIO_AON_PIN2_ALT_CTL_HDMI_5V, + GIO_AON_PIN2_ALT_FL0, + GIO_AON_PIN2_ALT_AON_PWM, + GIO_AON_PIN2_ALT_IR_IN, + GIO_AON_PIN2_ALT_VC_PWM1, +} GIO_AON_PIN2_ALT; + +typedef enum { + GIO_AON_PIN3_ALT_IR_IN = 1, + GIO_AON_PIN3_ALT_VC_SPI0, + GIO_AON_PIN3_ALT_VC_UART3, + GIO_AON_PIN3_ALT_AON_FP_4SEC_RESETB, + GIO_AON_PIN3_ALT_FL1, + GIO_AON_PIN3_ALT_SD_CARD_G, + GIO_AON_PIN3_ALT_AON_GPCLK, +} GIO_AON_PIN3_ALT; + +typedef enum { + GIO_AON_PIN4_ALT_GPCLK0 = 1, + GIO_AON_PIN4_ALT_VC_SPI0, + GIO_AON_PIN4_ALT_VC_I2CSL, + GIO_AON_PIN4_ALT_AON_GPCLK, + GIO_AON_PIN4_ALT_PM_LED_OUT, + GIO_AON_PIN4_ALT_AON_PWM, + GIO_AON_PIN4_ALT_SD_CARD_G, + GIO_AON_PIN4_ALT_VC_PWM0, +} GIO_AON_PIN4_ALT; + +typedef enum { + GIO_AON_PIN5_ALT_GPCLK1 = 1, + GIO_AON_PIN5_ALT_IR_IN, + GIO_AON_PIN5_ALT_VC_I2CSL, + GIO_AON_PIN5_ALT_CLK_OBSERVE, + GIO_AON_PIN5_ALT_AON_PWM, + GIO_AON_PIN5_ALT_SD_CARD_G, + GIO_AON_PIN5_ALT_VC_PWM0, +} GIO_AON_PIN5_ALT; + +typedef enum { + GIO_AON_PIN6_ALT_UART1 = 1, + GIO_AON_PIN6_ALT_VC_UART4, + GIO_AON_PIN6_ALT_GPCLK2, + GIO_AON_PIN6_ALT_CTL_HDMI_5V, + GIO_AON_PIN6_ALT_VC_UART0, + GIO_AON_PIN6_ALT_VC_SPI3, +} GIO_AON_PIN6_ALT; + +typedef enum { + GIO_AON_PIN7_ALT_UART1 = 1, + GIO_AON_PIN7_ALT_VC_UART4, + GIO_AON_PIN7_ALT_GPCLK0, + GIO_AON_PIN7_ALT_AON_PWM, + GIO_AON_PIN7_ALT_VC_UART0, + GIO_AON_PIN7_ALT_VC_SPI3, +} GIO_AON_PIN7_ALT; + +typedef enum { + GIO_AON_PIN8_ALT_UART1 = 1, + GIO_AON_PIN8_ALT_VC_UART4, + GIO_AON_PIN8_ALT_VC_I2CSL, + GIO_AON_PIN8_ALT_CTL_HDMI_5V, + GIO_AON_PIN8_ALT_VC_UART0, + GIO_AON_PIN8_ALT_VC_SPI3, +} GIO_AON_PIN8_ALT; + +typedef enum { + GIO_AON_PIN9_ALT_UART1 = 1, + GIO_AON_PIN9_ALT_VC_UART4, + GIO_AON_PIN9_ALT_VC_I2CSL, + GIO_AON_PIN9_ALT_AON_PWM, + GIO_AON_PIN9_ALT_VC_UART0, + GIO_AON_PIN9_ALT_VC_SPI3, +} GIO_AON_PIN9_ALT; + +typedef enum { + GIO_AON_PIN10_ALT_TSIO = 1, + GIO_AON_PIN10_ALT_CTL_HDMI_5V, + GIO_AON_PIN10_ALT_SC0, + GIO_AON_PIN10_ALT_SPDIF_OUT, + GIO_AON_PIN10_ALT_VC_SPI5, + GIO_AON_PIN10_ALT_USB_PWR, + GIO_AON_PIN10_ALT_AON_GPCLK, + GIO_AON_PIN10_ALT_SD_CARD_F, +} GIO_AON_PIN10_ALT; + +typedef enum { + GIO_AON_PIN11_ALT_TSIO = 1, + GIO_AON_PIN11_ALT_UART0, + GIO_AON_PIN11_ALT_SC0, + GIO_AON_PIN11_ALT_AUD_FS_CLK0, + GIO_AON_PIN11_ALT_VC_SPI5, + GIO_AON_PIN11_ALT_USB_VBUS, + GIO_AON_PIN11_ALT_VC_UART2, + GIO_AON_PIN11_ALT_SD_CARD_F, +} GIO_AON_PIN11_ALT; + +typedef enum { + GIO_AON_PIN12_ALT_TSIO = 1, + GIO_AON_PIN12_ALT_UART0, + GIO_AON_PIN12_ALT_VC_UART0, + GIO_AON_PIN12_ALT_TSIO_2, + GIO_AON_PIN12_ALT_VC_SPI5, + GIO_AON_PIN12_ALT_USB_PWR, + GIO_AON_PIN12_ALT_VC_UART2, + GIO_AON_PIN12_ALT_SD_CARD_F, +} GIO_AON_PIN12_ALT; + +typedef enum { + GIO_AON_PIN13_ALT_BSC_M1 = 1, + GIO_AON_PIN13_ALT_UART0, + GIO_AON_PIN13_ALT_VC_UART0, + GIO_AON_PIN13_ALT_UUI, + GIO_AON_PIN13_ALT_VC_SPI5, + GIO_AON_PIN13_ALT_ARM_JTAG, + GIO_AON_PIN13_ALT_VC_UART2, + GIO_AON_PIN13_ALT_VC_I2C3, +} GIO_AON_PIN13_ALT; + +typedef enum { + GIO_AON_PIN14_ALT_BSC_M1 = 1, + GIO_AON_PIN14_ALT_UART0, + GIO_AON_PIN14_ALT_VC_UART0, + GIO_AON_PIN14_ALT_UUI, + GIO_AON_PIN14_ALT_VC_SPI5, + GIO_AON_PIN14_ALT_ARM_JTAG, + GIO_AON_PIN14_ALT_VC_UART2, + GIO_AON_PIN14_ALT_VC_I2C3, +} GIO_AON_PIN14_ALT; + +typedef enum { + GIO_AON_PIN15_ALT_IR_IN = 1, + GIO_AON_PIN15_ALT_AON_FP_4SEC_RESETB, + GIO_AON_PIN15_ALT_VC_UART0, + GIO_AON_PIN15_ALT_PM_LED_OUT, + GIO_AON_PIN15_ALT_CTL_HDMI_5V, + GIO_AON_PIN15_ALT_AON_PWM, + GIO_AON_PIN15_ALT_AON_GPCLK, +} GIO_AON_PIN15_ALT; + +typedef enum { + GIO_AON_PIN16_ALT_AON_CPU_STANDBYB = 1, + GIO_AON_PIN16_ALT_GPCLK0, + GIO_AON_PIN16_ALT_PM_LED_OUT, + GIO_AON_PIN16_ALT_CTL_HDMI_5V, + GIO_AON_PIN16_ALT_VC_PWM0, + GIO_AON_PIN16_ALT_USB_PWR, + GIO_AON_PIN16_ALT_AUD_FS_CLK0, +} GIO_AON_PIN16_ALT; + +typedef enum { + GIO_AON_PIN17_ALT_HDMI_TX0_BSC = 1, + GIO_AON_PIN17_ALT_HDMI_TX0_AUTO_I2C, + GIO_AON_PIN17_ALT_BSC_M0, + GIO_AON_PIN17_ALT_VC_I2C0, +} GIO_AON_PIN17_ALT; + +typedef enum { + GIO_AON_PIN18_ALT_HDMI_TX0_BSC = 1, + GIO_AON_PIN18_ALT_HDMI_TX0_AUTO_I2C, + GIO_AON_PIN18_ALT_BSC_M0, + GIO_AON_PIN18_ALT_VC_I2C0, +} GIO_AON_PIN18_ALT; + +typedef enum { + GIO_AON_PIN19_ALT_HDMI_TX1_BSC = 1, + GIO_AON_PIN19_ALT_HDMI_TX1_AUTO_I2C, + GIO_AON_PIN19_ALT_BSC_M1, + GIO_AON_PIN19_ALT_VC_I2C4, + GIO_AON_PIN19_ALT_CTL_HDMI_5V, +} GIO_AON_PIN19_ALT; + +typedef enum { + GIO_AON_PIN20_ALT_HDMI_TX1_BSC = 1, + GIO_AON_PIN20_ALT_HDMI_TX1_AUTO_I2C, + GIO_AON_PIN20_ALT_BSC_M1, + GIO_AON_PIN20_ALT_VC_I2C4, +} GIO_AON_PIN20_ALT; + +typedef enum { + GIO_AON_PIN21_ALT_AVS_PMU_BSC = 1, + GIO_AON_PIN21_ALT_BSC_M2, + GIO_AON_PIN21_ALT_VC_I2C5, + GIO_AON_PIN21_ALT_CTL_HDMI_5V, +} GIO_AON_PIN21_ALT; + +typedef enum { + GIO_AON_PIN22_ALT_AVS_PMU_BSC = 1, + GIO_AON_PIN22_ALT_BSC_M2, + GIO_AON_PIN22_ALT_VC_I2C5, +} GIO_AON_PIN22_ALT; + +#endif // __BCM2712_PINCTRL_H__ diff --git a/Silicon/Broadcom/Bcm27xx/Include/Library/Bcm2712GpioLib.h b/Silicon/Broadcom/Bcm27xx/Include/Library/Bcm2712GpioLib.h new file mode 100644 index 00000000..6109fccc --- /dev/null +++ b/Silicon/Broadcom/Bcm27xx/Include/Library/Bcm2712GpioLib.h @@ -0,0 +1,103 @@ +/** @file + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + + +#ifndef __BCM2712_GPIO_LIB_H__ +#define __BCM2712_GPIO_LIB_H__ + +typedef enum { + BCM2712_GIO = 0, + BCM2712_GIO_AON, + BCM2712_GIO_COUNT +} BCM2712_GPIO_TYPE; + +typedef enum { + BCM2712_GPIO_ALT_IO = 0, + BCM2712_GPIO_ALT_1, + BCM2712_GPIO_ALT_2, + BCM2712_GPIO_ALT_3, + BCM2712_GPIO_ALT_4, + BCM2712_GPIO_ALT_5, + BCM2712_GPIO_ALT_6, + BCM2712_GPIO_ALT_7, + BCM2712_GPIO_ALT_8, + BCM2712_GPIO_ALT_COUNT +} BCM2712_GPIO_ALT; + +typedef enum { + BCM2712_GPIO_PIN_PULL_NONE = 0, + BCM2712_GPIO_PIN_PULL_DOWN = 1, + BCM2712_GPIO_PIN_PULL_UP = 2 +} BCM2712_GPIO_PIN_PULL; + +typedef enum { + BCM2712_GPIO_PIN_OUTPUT = 0, + BCM2712_GPIO_PIN_INPUT = 1 +} BCM2712_GPIO_PIN_DIRECTION; + +UINT8 +EFIAPI +GpioGetFunction ( + IN BCM2712_GPIO_TYPE Type, + IN UINT8 Pin + ); + +VOID +EFIAPI +GpioSetFunction ( + IN BCM2712_GPIO_TYPE Type, + IN UINT8 Pin, + IN UINT8 Function + ); + +BCM2712_GPIO_PIN_PULL +EFIAPI +GpioGetPull ( + IN BCM2712_GPIO_TYPE Type, + IN UINT8 Pin + ); + +VOID +EFIAPI +GpioSetPull ( + IN BCM2712_GPIO_TYPE Type, + IN UINT8 Pin, + IN BCM2712_GPIO_PIN_PULL Pull + ); + +BOOLEAN +EFIAPI +GpioRead ( + IN BCM2712_GPIO_TYPE Type, + IN UINT8 Pin + ); + +VOID +EFIAPI +GpioWrite ( + IN BCM2712_GPIO_TYPE Type, + IN UINT8 Pin, + IN BOOLEAN Value + ); + +BCM2712_GPIO_PIN_DIRECTION +EFIAPI +GpioGetDirection ( + IN BCM2712_GPIO_TYPE Type, + IN UINT8 Pin + ); + +VOID +EFIAPI +GpioSetDirection ( + IN BCM2712_GPIO_TYPE Type, + IN UINT8 Pin, + IN BCM2712_GPIO_PIN_DIRECTION Direction + ); + +#endif // __BCM2712_GPIO_LIB_H__ diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2712GpioLib/Bcm2712GpioLib.c b/Silicon/Broadcom/Bcm27xx/Library/Bcm2712GpioLib/Bcm2712GpioLib.c new file mode 100644 index 00000000..2d9019ed --- /dev/null +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2712GpioLib/Bcm2712GpioLib.c @@ -0,0 +1,375 @@ +/** @file + * + * Copyright (c) 2023, Mario Bălănică + * + * SPDX-License-Identifier: BSD-2-Clause-Patent + * + **/ + +#include +#include +#include +#include +#include + +#define BCM2712_GIO_DATA_REG 0x4 +#define BCM2712_GIO_IODIR_REG 0x8 + +#define BCM2712_GIO_BANK_SIZE (8 * sizeof (UINT32)) +#define BCM2712_GIO_MAX_PINS_PER_BANK 32 + +#define BCM2712_GIO_BANK_OFFSET(Pin) ((Pin / BCM2712_GIO_MAX_PINS_PER_BANK) * BCM2712_GIO_BANK_SIZE) +#define BCM2712_GIO_REG_BIT(Pin) (1 << Pin) + +#define BCM2712_PINCTRL_FSEL_MASK (BIT3 | BIT2 | BIT1 | BIT0) +#define BCM2712_PINCTRL_PULL_MASK (BIT1 | BIT0) + +#define PINCTRL_REG_UNUSED MAX_UINT16 + +typedef struct { + UINT16 MuxReg; + UINT8 MuxBit; + UINT16 CtlReg; + UINT8 CtlBit; +} BCM2712_PINCTRL_REGISTERS; + +typedef struct { + EFI_PHYSICAL_ADDRESS GioBase; + EFI_PHYSICAL_ADDRESS PinctrlBase; + BCM2712_PINCTRL_REGISTERS *PinctrlRegisters; + UINT32 PinCount; +} BCM2712_GPIO_CONTROLLER; + +STATIC BCM2712_PINCTRL_REGISTERS Bcm2712PinctrlGioRegisters[] = { + [0] = { .MuxReg = 0x0, .MuxBit = 0, .CtlReg = 0x1C, .CtlBit = 14 }, + [1] = { .MuxReg = 0x0, .MuxBit = 4, .CtlReg = 0x1C, .CtlBit = 16 }, + [2] = { .MuxReg = 0x0, .MuxBit = 8, .CtlReg = 0x1C, .CtlBit = 18 }, + [3] = { .MuxReg = 0x0, .MuxBit = 12, .CtlReg = 0x1C, .CtlBit = 20 }, + [4] = { .MuxReg = 0x0, .MuxBit = 16, .CtlReg = 0x1C, .CtlBit = 22 }, + [5] = { .MuxReg = 0x0, .MuxBit = 20, .CtlReg = 0x1C, .CtlBit = 24 }, + [6] = { .MuxReg = 0x0, .MuxBit = 24, .CtlReg = 0x1C, .CtlBit = 26 }, + [7] = { .MuxReg = 0x0, .MuxBit = 28, .CtlReg = 0x1C, .CtlBit = 28 }, + [8] = { .MuxReg = 0x4, .MuxBit = 0, .CtlReg = 0x20, .CtlBit = 0 }, + [9] = { .MuxReg = 0x4, .MuxBit = 4, .CtlReg = 0x20, .CtlBit = 2 }, + [10] = { .MuxReg = 0x4, .MuxBit = 8, .CtlReg = 0x20, .CtlBit = 4 }, + [11] = { .MuxReg = 0x4, .MuxBit = 12, .CtlReg = 0x20, .CtlBit = 6 }, + [12] = { .MuxReg = 0x4, .MuxBit = 16, .CtlReg = 0x20, .CtlBit = 8 }, + [13] = { .MuxReg = 0x4, .MuxBit = 20, .CtlReg = 0x20, .CtlBit = 10 }, + [14] = { .MuxReg = 0x4, .MuxBit = 24, .CtlReg = 0x20, .CtlBit = 12 }, + [15] = { .MuxReg = 0x4, .MuxBit = 28, .CtlReg = 0x20, .CtlBit = 14 }, + [16] = { .MuxReg = 0x8, .MuxBit = 0, .CtlReg = 0x20, .CtlBit = 16 }, + [17] = { .MuxReg = 0x8, .MuxBit = 4, .CtlReg = 0x20, .CtlBit = 18 }, + [18] = { .MuxReg = 0x8, .MuxBit = 8, .CtlReg = 0x20, .CtlBit = 20 }, + [19] = { .MuxReg = 0x8, .MuxBit = 12, .CtlReg = 0x20, .CtlBit = 22 }, + [20] = { .MuxReg = 0x8, .MuxBit = 16, .CtlReg = 0x20, .CtlBit = 24 }, + [21] = { .MuxReg = 0x8, .MuxBit = 20, .CtlReg = 0x20, .CtlBit = 26 }, + [22] = { .MuxReg = 0x8, .MuxBit = 24, .CtlReg = 0x20, .CtlBit = 28 }, + [23] = { .MuxReg = 0x8, .MuxBit = 28, .CtlReg = 0x24, .CtlBit = 0 }, + [24] = { .MuxReg = 0xC, .MuxBit = 0, .CtlReg = 0x24, .CtlBit = 2 }, + [25] = { .MuxReg = 0xC, .MuxBit = 4, .CtlReg = 0x24, .CtlBit = 4 }, + [26] = { .MuxReg = 0xC, .MuxBit = 8, .CtlReg = 0x24, .CtlBit = 6 }, + [27] = { .MuxReg = 0xC, .MuxBit = 12, .CtlReg = 0x24, .CtlBit = 8 }, + [28] = { .MuxReg = 0xC, .MuxBit = 16, .CtlReg = 0x24, .CtlBit = 10 }, + [29] = { .MuxReg = 0xC, .MuxBit = 20, .CtlReg = 0x24, .CtlBit = 12 }, + [30] = { .MuxReg = 0xC, .MuxBit = 24, .CtlReg = 0x24, .CtlBit = 14 }, + [31] = { .MuxReg = 0xC, .MuxBit = 28, .CtlReg = 0x24, .CtlBit = 16 }, + [32] = { .MuxReg = 0x10, .MuxBit = 0, .CtlReg = 0x24, .CtlBit = 18 }, + [33] = { .MuxReg = 0x10, .MuxBit = 4, .CtlReg = 0x24, .CtlBit = 20 }, + [34] = { .MuxReg = 0x10, .MuxBit = 8, .CtlReg = 0x24, .CtlBit = 22 }, + [35] = { .MuxReg = 0x10, .MuxBit = 12, .CtlReg = 0x24, .CtlBit = 24 }, + [36] = { .MuxReg = 0x10, .MuxBit = 16, .CtlReg = 0x24, .CtlBit = 26 }, + [37] = { .MuxReg = 0x10, .MuxBit = 20, .CtlReg = 0x24, .CtlBit = 28 }, + [38] = { .MuxReg = 0x10, .MuxBit = 24, .CtlReg = 0x28, .CtlBit = 0 }, + [39] = { .MuxReg = 0x10, .MuxBit = 28, .CtlReg = 0x28, .CtlBit = 2 }, + [40] = { .MuxReg = 0x14, .MuxBit = 0, .CtlReg = 0x28, .CtlBit = 4 }, + [41] = { .MuxReg = 0x14, .MuxBit = 4, .CtlReg = 0x28, .CtlBit = 6 }, + [42] = { .MuxReg = 0x14, .MuxBit = 8, .CtlReg = 0x28, .CtlBit = 8 }, + [43] = { .MuxReg = 0x14, .MuxBit = 12, .CtlReg = 0x28, .CtlBit = 10 }, + [44] = { .MuxReg = 0x14, .MuxBit = 16, .CtlReg = 0x28, .CtlBit = 12 }, + [45] = { .MuxReg = 0x14, .MuxBit = 20, .CtlReg = 0x28, .CtlBit = 14 }, + [46] = { .MuxReg = 0x14, .MuxBit = 24, .CtlReg = 0x28, .CtlBit = 16 }, + [47] = { .MuxReg = 0x14, .MuxBit = 28, .CtlReg = 0x28, .CtlBit = 18 }, + [48] = { .MuxReg = 0x18, .MuxBit = 0, .CtlReg = 0x28, .CtlBit = 20 }, + [49] = { .MuxReg = 0x18, .MuxBit = 4, .CtlReg = 0x28, .CtlBit = 22 }, + [50] = { .MuxReg = 0x18, .MuxBit = 8, .CtlReg = 0x28, .CtlBit = 24 }, + [51] = { .MuxReg = 0x18, .MuxBit = 12, .CtlReg = 0x28, .CtlBit = 26 }, + [52] = { .MuxReg = 0x18, .MuxBit = 16, .CtlReg = 0x28, .CtlBit = 28 }, + [53] = { .MuxReg = 0x18, .MuxBit = 20, .CtlReg = 0x2C, .CtlBit = 0 }, + [54] = { .MuxReg = PINCTRL_REG_UNUSED, .MuxBit = 0, .CtlReg = 0x2C, .CtlBit = 2 }, + [55] = { .MuxReg = PINCTRL_REG_UNUSED, .MuxBit = 0, .CtlReg = 0x2C, .CtlBit = 4 }, + [56] = { .MuxReg = PINCTRL_REG_UNUSED, .MuxBit = 0, .CtlReg = 0x2C, .CtlBit = 6 }, + [57] = { .MuxReg = PINCTRL_REG_UNUSED, .MuxBit = 0, .CtlReg = 0x2C, .CtlBit = 8 }, + [58] = { .MuxReg = PINCTRL_REG_UNUSED, .MuxBit = 0, .CtlReg = 0x2C, .CtlBit = 10 }, + [59] = { .MuxReg = PINCTRL_REG_UNUSED, .MuxBit = 0, .CtlReg = 0x2C, .CtlBit = 12 }, + [60] = { .MuxReg = PINCTRL_REG_UNUSED, .MuxBit = 0, .CtlReg = 0x2C, .CtlBit = 14 }, + [61] = { .MuxReg = PINCTRL_REG_UNUSED, .MuxBit = 0, .CtlReg = 0x2C, .CtlBit = 16 }, + [62] = { .MuxReg = PINCTRL_REG_UNUSED, .MuxBit = 0, .CtlReg = 0x2C, .CtlBit = 18 }, + [63] = { .MuxReg = PINCTRL_REG_UNUSED, .MuxBit = 0, .CtlReg = 0x2C, .CtlBit = 20 }, + [64] = { .MuxReg = PINCTRL_REG_UNUSED, .MuxBit = 0, .CtlReg = 0x2C, .CtlBit = 22 }, +}; + +STATIC BCM2712_PINCTRL_REGISTERS Bcm2712PinctrlGioAonRegisters[] = { + [0] = { .MuxReg = 0xC, .MuxBit = 0, .CtlReg = 0x18, .CtlBit = 20 }, + [1] = { .MuxReg = 0xC, .MuxBit = 4, .CtlReg = 0x18, .CtlBit = 22 }, + [2] = { .MuxReg = 0xC, .MuxBit = 8, .CtlReg = 0x18, .CtlBit = 24 }, + [3] = { .MuxReg = 0xC, .MuxBit = 12, .CtlReg = 0x18, .CtlBit = 26 }, + [4] = { .MuxReg = 0xC, .MuxBit = 16, .CtlReg = 0x18, .CtlBit = 28 }, + [5] = { .MuxReg = 0xC, .MuxBit = 20, .CtlReg = 0x1C, .CtlBit = 0 }, + [6] = { .MuxReg = 0xC, .MuxBit = 24, .CtlReg = 0x1C, .CtlBit = 2 }, + [7] = { .MuxReg = 0xC, .MuxBit = 28, .CtlReg = 0x1C, .CtlBit = 4 }, + [8] = { .MuxReg = 0x10, .MuxBit = 0, .CtlReg = 0x1C, .CtlBit = 6 }, + [9] = { .MuxReg = 0x10, .MuxBit = 4, .CtlReg = 0x1C, .CtlBit = 8 }, + [10] = { .MuxReg = 0x10, .MuxBit = 8, .CtlReg = 0x1C, .CtlBit = 10 }, + [11] = { .MuxReg = 0x10, .MuxBit = 12, .CtlReg = 0x1C, .CtlBit = 12 }, + [12] = { .MuxReg = 0x10, .MuxBit = 16, .CtlReg = 0x1C, .CtlBit = 14 }, + [13] = { .MuxReg = 0x10, .MuxBit = 20, .CtlReg = 0x1C, .CtlBit = 16 }, + [14] = { .MuxReg = 0x10, .MuxBit = 24, .CtlReg = 0x1C, .CtlBit = 18 }, + [15] = { .MuxReg = 0x10, .MuxBit = 28, .CtlReg = 0x1C, .CtlBit = 20 }, + [16] = { .MuxReg = 0x14, .MuxBit = 0, .CtlReg = 0x1C, .CtlBit = 22 }, + [17] = { .MuxReg = PINCTRL_REG_UNUSED, .MuxBit = 0, .CtlReg = PINCTRL_REG_UNUSED, .CtlBit = 0 }, + [18] = { .MuxReg = PINCTRL_REG_UNUSED, .MuxBit = 0, .CtlReg = PINCTRL_REG_UNUSED, .CtlBit = 0 }, + [19] = { .MuxReg = PINCTRL_REG_UNUSED, .MuxBit = 0, .CtlReg = PINCTRL_REG_UNUSED, .CtlBit = 0 }, + [20] = { .MuxReg = PINCTRL_REG_UNUSED, .MuxBit = 0, .CtlReg = PINCTRL_REG_UNUSED, .CtlBit = 0 }, + [21] = { .MuxReg = PINCTRL_REG_UNUSED, .MuxBit = 0, .CtlReg = PINCTRL_REG_UNUSED, .CtlBit = 0 }, + [22] = { .MuxReg = PINCTRL_REG_UNUSED, .MuxBit = 0, .CtlReg = PINCTRL_REG_UNUSED, .CtlBit = 0 }, + [23] = { .MuxReg = PINCTRL_REG_UNUSED, .MuxBit = 0, .CtlReg = PINCTRL_REG_UNUSED, .CtlBit = 0 }, + [24] = { .MuxReg = PINCTRL_REG_UNUSED, .MuxBit = 0, .CtlReg = PINCTRL_REG_UNUSED, .CtlBit = 0 }, + [25] = { .MuxReg = PINCTRL_REG_UNUSED, .MuxBit = 0, .CtlReg = PINCTRL_REG_UNUSED, .CtlBit = 0 }, + [26] = { .MuxReg = PINCTRL_REG_UNUSED, .MuxBit = 0, .CtlReg = PINCTRL_REG_UNUSED, .CtlBit = 0 }, + [27] = { .MuxReg = PINCTRL_REG_UNUSED, .MuxBit = 0, .CtlReg = PINCTRL_REG_UNUSED, .CtlBit = 0 }, + [28] = { .MuxReg = PINCTRL_REG_UNUSED, .MuxBit = 0, .CtlReg = PINCTRL_REG_UNUSED, .CtlBit = 0 }, + [29] = { .MuxReg = PINCTRL_REG_UNUSED, .MuxBit = 0, .CtlReg = PINCTRL_REG_UNUSED, .CtlBit = 0 }, + [30] = { .MuxReg = PINCTRL_REG_UNUSED, .MuxBit = 0, .CtlReg = PINCTRL_REG_UNUSED, .CtlBit = 0 }, + [31] = { .MuxReg = PINCTRL_REG_UNUSED, .MuxBit = 0, .CtlReg = PINCTRL_REG_UNUSED, .CtlBit = 0 }, + [32] = { .MuxReg = 0x0, .MuxBit = 0, .CtlReg = PINCTRL_REG_UNUSED, .CtlBit = 0 }, + [33] = { .MuxReg = 0x0, .MuxBit = 4, .CtlReg = PINCTRL_REG_UNUSED, .CtlBit = 0 }, + [34] = { .MuxReg = 0x0, .MuxBit = 8, .CtlReg = PINCTRL_REG_UNUSED, .CtlBit = 0 }, + [35] = { .MuxReg = 0x0, .MuxBit = 12, .CtlReg = PINCTRL_REG_UNUSED, .CtlBit = 0 }, + [36] = { .MuxReg = 0x4, .MuxBit = 0, .CtlReg = PINCTRL_REG_UNUSED, .CtlBit = 0 }, + [37] = { .MuxReg = 0x8, .MuxBit = 0, .CtlReg = PINCTRL_REG_UNUSED, .CtlBit = 0 }, +}; + +STATIC BCM2712_GPIO_CONTROLLER Controllers[BCM2712_GIO_COUNT] = { + { + .GioBase = BCM2712_BRCMSTB_GIO_BASE, + .PinctrlBase = BCM2712_PINCTRL_BASE, + .PinctrlRegisters = Bcm2712PinctrlGioRegisters, + .PinCount = ARRAY_SIZE (Bcm2712PinctrlGioRegisters) + }, { + .GioBase = BCM2712_BRCMSTB_GIO_AON_BASE, + .PinctrlBase = BCM2712_PINCTRL_AON_BASE, + .PinctrlRegisters = Bcm2712PinctrlGioAonRegisters, + .PinCount = ARRAY_SIZE (Bcm2712PinctrlGioAonRegisters) + } +}; + +#define GPIOLIB_ASSERT_OR_FAIL(Expression, FailAction) \ + do { \ + ASSERT(Expression); \ + if (!(Expression)) { \ + FailAction; \ + } \ + } while (FALSE) + +#define GPIOLIB_ASSERT_COMMON_PARAMS(Type, Pin, FailAction) \ + GPIOLIB_ASSERT_OR_FAIL ((Type < ARRAY_SIZE (Controllers)) \ + && (Pin < Controllers[Type].PinCount), \ + FailAction) + +UINT8 +EFIAPI +GpioGetFunction ( + IN BCM2712_GPIO_TYPE Type, + IN UINT8 Pin + ) +{ + BCM2712_GPIO_CONTROLLER *Controller; + BCM2712_PINCTRL_REGISTERS *Regs; + UINT32 Value = BCM2712_GPIO_ALT_COUNT; + + GPIOLIB_ASSERT_COMMON_PARAMS (Type, Pin, return Value); + + Controller = &Controllers[Type]; + Regs = &Controller->PinctrlRegisters[Pin]; + + GPIOLIB_ASSERT_OR_FAIL (Regs->MuxReg != PINCTRL_REG_UNUSED, return Value); + + Value = MmioRead32 (Controller->PinctrlBase + Regs->MuxReg); + + return (Value >> Regs->MuxBit) & BCM2712_PINCTRL_FSEL_MASK; +} + +VOID +EFIAPI +GpioSetFunction ( + IN BCM2712_GPIO_TYPE Type, + IN UINT8 Pin, + IN UINT8 Function + ) +{ + BCM2712_GPIO_CONTROLLER *Controller; + BCM2712_PINCTRL_REGISTERS *Regs; + + GPIOLIB_ASSERT_COMMON_PARAMS (Type, Pin, return); + + Controller = &Controllers[Type]; + Regs = &Controller->PinctrlRegisters[Pin]; + + GPIOLIB_ASSERT_OR_FAIL (Regs->MuxReg != PINCTRL_REG_UNUSED, return); + + MmioAndThenOr32 (Controller->PinctrlBase + Regs->MuxReg, + ~(BCM2712_PINCTRL_FSEL_MASK << Regs->MuxBit), + Function << Regs->MuxBit); +} + +BCM2712_GPIO_PIN_PULL +EFIAPI +GpioGetPull ( + IN BCM2712_GPIO_TYPE Type, + IN UINT8 Pin + ) +{ + BCM2712_GPIO_CONTROLLER *Controller; + BCM2712_PINCTRL_REGISTERS *Regs; + UINT32 Value = BCM2712_GPIO_PIN_PULL_NONE; + + GPIOLIB_ASSERT_COMMON_PARAMS (Type, Pin, return Value); + + Controller = &Controllers[Type]; + Regs = &Controller->PinctrlRegisters[Pin]; + + GPIOLIB_ASSERT_OR_FAIL (Regs->CtlReg != PINCTRL_REG_UNUSED, return Value); + + Value = MmioRead32 (Controller->PinctrlBase + Regs->CtlReg); + + return (Value >> Regs->CtlBit) & BCM2712_PINCTRL_PULL_MASK; +} + +VOID +EFIAPI +GpioSetPull ( + IN BCM2712_GPIO_TYPE Type, + IN UINT8 Pin, + IN BCM2712_GPIO_PIN_PULL Pull + ) +{ + BCM2712_GPIO_CONTROLLER *Controller; + BCM2712_PINCTRL_REGISTERS *Regs; + + GPIOLIB_ASSERT_COMMON_PARAMS (Type, Pin, return); + + Controller = &Controllers[Type]; + Regs = &Controller->PinctrlRegisters[Pin]; + + GPIOLIB_ASSERT_OR_FAIL (Pull == BCM2712_GPIO_PIN_PULL_NONE + || Pull == BCM2712_GPIO_PIN_PULL_UP + || Pull == BCM2712_GPIO_PIN_PULL_DOWN, + return); + + GPIOLIB_ASSERT_OR_FAIL (Regs->CtlReg != PINCTRL_REG_UNUSED, return); + + MmioAndThenOr32 (Controller->PinctrlBase + Regs->CtlReg, + ~(BCM2712_PINCTRL_PULL_MASK << Regs->CtlBit), + Pull << Regs->CtlBit); +} + +BOOLEAN +EFIAPI +GpioRead ( + IN BCM2712_GPIO_TYPE Type, + IN UINT8 Pin + ) +{ + BCM2712_GPIO_CONTROLLER *Controller; + EFI_PHYSICAL_ADDRESS BankReg; + UINT32 Value = FALSE; + + GPIOLIB_ASSERT_COMMON_PARAMS (Type, Pin, return Value); + + Controller = &Controllers[Type]; + BankReg = Controller->GioBase + BCM2712_GIO_BANK_OFFSET (Pin); + + Value = MmioRead32 (BankReg + BCM2712_GIO_DATA_REG); + + return (Value & BCM2712_GIO_REG_BIT (Pin)) != 0; +} + +VOID +EFIAPI +GpioWrite ( + IN BCM2712_GPIO_TYPE Type, + IN UINT8 Pin, + IN BOOLEAN Value + ) +{ + BCM2712_GPIO_CONTROLLER *Controller; + EFI_PHYSICAL_ADDRESS BankReg; + + GPIOLIB_ASSERT_COMMON_PARAMS (Type, Pin, return); + + Controller = &Controllers[Type]; + BankReg = Controller->GioBase + BCM2712_GIO_BANK_OFFSET (Pin); + + if (Value) { + MmioOr32 (BankReg + BCM2712_GIO_DATA_REG, BCM2712_GIO_REG_BIT (Pin)); + } else { + MmioAnd32 (BankReg + BCM2712_GIO_DATA_REG, ~BCM2712_GIO_REG_BIT (Pin)); + } +} + +BCM2712_GPIO_PIN_DIRECTION +EFIAPI +GpioGetDirection ( + IN BCM2712_GPIO_TYPE Type, + IN UINT8 Pin + ) +{ + BCM2712_GPIO_CONTROLLER *Controller; + EFI_PHYSICAL_ADDRESS BankReg; + UINT32 Value = BCM2712_GPIO_PIN_OUTPUT; + + GPIOLIB_ASSERT_COMMON_PARAMS (Type, Pin, return Value); + + Controller = &Controllers[Type]; + BankReg = Controller->GioBase + BCM2712_GIO_BANK_OFFSET (Pin); + + Value = MmioRead32 (BankReg + BCM2712_GIO_IODIR_REG); + + if (Value & BCM2712_GIO_REG_BIT (Pin)) { + return BCM2712_GPIO_PIN_INPUT; + } else { + return BCM2712_GPIO_PIN_OUTPUT; + } +} + +VOID +EFIAPI +GpioSetDirection ( + IN BCM2712_GPIO_TYPE Type, + IN UINT8 Pin, + IN BCM2712_GPIO_PIN_DIRECTION Direction + ) +{ + BCM2712_GPIO_CONTROLLER *Controller; + EFI_PHYSICAL_ADDRESS BankReg; + + GPIOLIB_ASSERT_COMMON_PARAMS (Type, Pin, return); + + GPIOLIB_ASSERT_OR_FAIL (Direction != BCM2712_GPIO_PIN_OUTPUT + || Direction != BCM2712_GPIO_PIN_INPUT, + return); + + Controller = &Controllers[Type]; + BankReg = Controller->GioBase + BCM2712_GIO_BANK_OFFSET (Pin); + + switch (Direction) { + case BCM2712_GPIO_PIN_INPUT: + MmioOr32 (BankReg + BCM2712_GIO_IODIR_REG, BCM2712_GIO_REG_BIT (Pin)); + break; + case BCM2712_GPIO_PIN_OUTPUT: + MmioAnd32 (BankReg + BCM2712_GIO_IODIR_REG, ~BCM2712_GIO_REG_BIT (Pin)); + break; + default: + break; + } +} diff --git a/Silicon/Broadcom/Bcm27xx/Library/Bcm2712GpioLib/Bcm2712GpioLib.inf b/Silicon/Broadcom/Bcm27xx/Library/Bcm2712GpioLib/Bcm2712GpioLib.inf new file mode 100644 index 00000000..821c0190 --- /dev/null +++ b/Silicon/Broadcom/Bcm27xx/Library/Bcm2712GpioLib/Bcm2712GpioLib.inf @@ -0,0 +1,26 @@ +#/** @file +# +# Copyright (c) 2023, Mario Bălănică +# +# SPDX-License-Identifier: BSD-2-Clause-Patent +# +#**/ + +[Defines] + INF_VERSION = 0x0001001A + BASE_NAME = Bcm2712GpioLib + FILE_GUID = 86a00ea0-6c21-4408-b8c7-3ae675c4678b + MODULE_TYPE = BASE + VERSION_STRING = 1.0 + LIBRARY_CLASS = Bcm2712GpioLib + +[Sources] + Bcm2712GpioLib.c + +[Packages] + MdePkg/MdePkg.dec + Silicon/Broadcom/Bcm27xx/Bcm27xx.dec + +[LibraryClasses] + DebugLib + IoLib -- 2.51.2