lmao perhaps

packages/linux-cachyos/prepare.nix

@@ -7,6 +7,10 @@
   kernel,
   ogKernelConfigfile,
   commonMakeFlags,
+  # Rust toolchain — only injected when cachyConfig.withRust is true
+  rustc ? null,
+  rustBindgen ? null,
+  rustLibSrc ? null,
 }:
 let
   version =
@@ -148,7 +152,8 @@ let
     ++ ntSyncConfig
     ++ hdrConfig
     ++ disableDebug
-    ++ pageSizeConfig;
+    ++ pageSizeConfig
+    ++ asahiPlatformConfig;
 
   # _cachy_config, defaults to "y"
   basicCachyConfig = lib.optional cachyConfig.basicCachy "-e CACHY";
@@ -406,6 +411,84 @@ let
     else
       throw "Unsupported cachyos _hugepage";
 
+  # Apple Silicon (Asahi) platform drivers
+  # Mirrors the options set in the asahi-alarm/PKGBUILDs linux-asahi config.
+  # ARCH_APPLE is the root Kconfig symbol; everything else gates on it.
+  # olddefconfig will auto-select most sub-options once ARCH_APPLE is on,
+  # but the hardware-specific drivers are listed explicitly so they aren't
+  # left as =m when we want them built-in, or omitted entirely.
+  asahiPlatformConfig = lib.optionals (cachyConfig.taste == "linux-cachyos-asahi") [
+    # Rust support — must come before any symbol that depends on it
+    "-e RUST"
+
+    # SoC platform — root symbol; must come first
+    "-e ARCH_APPLE"
+
+    # Interrupt controller
+    "-e APPLE_AIC"
+
+    # IOMMU (required for PCIe, GPU, and NVMe)
+    "-e APPLE_DART"
+
+    # RTKit coprocessor framework (required by GPU, audio, SEP)
+    "-e APPLE_RTKIT"
+    "-e APPLE_RTKIT_HELPER"
+    "-e APPLE_MAILBOX"
+    # Rust-based mailbox/rtkit (present in 6.18 Asahi tree)
+    "-e RUST_APPLE_MAILBOX"
+    "-e RUST_APPLE_RTKIT"
+
+    # Power management
+    "-e APPLE_PMGR_PWRSTATE"
+    "-e APPLE_PMGR_MISC"
+
+    # DMA controller (required by audio)
+    "-e APPLE_ADMAC"
+
+    # Security / SART (required by NVMe)
+    "-e APPLE_SART"
+    "-e APPLE_SEP"
+
+    # Storage
+    "-e NVME_APPLE"
+
+    # PCIe
+    "-e PCIE_APPLE"
+
+    # CPU frequency / idle
+    "-e ARM_APPLE_SOC_CPUFREQ"
+    "-e ARM_APPLE_CPUIDLE"
+
+    # Pin control
+    "-e PINCTRL_APPLE_GPIO"
+
+    # Display (DCP)
+    "-m DRM_APPLE"
+    "-e DRM_APPLE_AUDIO"
+
+    # GPU (Asahi AGX Rust driver)
+    "-e DRM_ASAHI"
+
+    # Audio
+    "-m SND_SOC_APPLE_MCA"
+    "-m SND_SOC_APPLE_MACAUDIO"
+    "-m SND_SOC_APPLE_AOP_AUDIO"
+
+    # Misc Apple SoC peripherals
+    "-e APPLE_DOCKCHANNEL"
+    "-e APPLE_WATCHDOG"
+    "-m APPLE_SIO"
+    "-m APPLE_AOP"
+    "-e APPLE_M1_CPU_PMU"
+
+    # 16K pages — Apple Silicon runs with 16K page granule
+    "-d ARM64_4K_PAGES"
+    "-e ARM64_16K_PAGES"
+
+    # NR_CPUS: Apple Silicon has at most ~16 cores; 64 is the Asahi default
+    "--set-val NR_CPUS 64"
+  ];
+
   # _damon, defaults to empty
   damonConfig = lib.optionals cachyConfig.withDAMON [
     "-e DAMON"
@@ -449,11 +532,19 @@ let
   configTaste =
     if cachyConfig.taste == "linux-cachyos-asahi" then "linux-cachyos-lts" else cachyConfig.taste;
 
+  # Rust toolchain — needed so `make olddefconfig` can probe rustc and set
+  # RUSTC_VERSION correctly, which gates CONFIG_RUST and all rust-dependent
+  # symbols (DRM_ASAHI, APPLE_SEP, etc.)
+  rustNativeBuildInputs = lib.optionals cachyConfig.withRust [
+    rustc
+    rustBindgen
+  ];
+
 in
 stdenv.mkDerivation (finalAttrs: {
   inherit src patches;
   name = "linux-cachyos-config";
-  nativeBuildInputs = kernel.nativeBuildInputs ++ kernel.buildInputs;
+  nativeBuildInputs = kernel.nativeBuildInputs ++ kernel.buildInputs ++ rustNativeBuildInputs;
 
   # Apply each patch with --forward (skip already-applied/reversed hunks) and
   # --fuzz=3 (tolerate minor context differences due to kernel version skew).
@@ -470,6 +561,11 @@ stdenv.mkDerivation (finalAttrs: {
 
   makeFlags = commonMakeFlags;
 
+  env = lib.optionalAttrs cachyConfig.withRust {
+    RUST_LIB_SRC = rustLibSrc;
+    KRUSTFLAGS = "--remap-path-prefix ${rustLibSrc}=/";
+  };
+
   postPhase = ''
     ${finalAttrs.passthru.extraVerPatch}
   '';